- A “Divide-by-Odd Number” Injection-Locked Frequency Divider. Matlab, Spice, Lab View and TSMC 65nm Cadence.
- Delay-Locked Loop Based Frequency Multiplier, VLSI Chip Design (CDIO Project Work), full custom design in 0.35um, taped out for fabrication and later on tested after fabrication. Cadence and Matlab.
- Mixed Signal Processing Systems, CDIO Project Work, designed DAC, ADC, Analog Filters and modeled Interpolator, Decimator and Channel. Cadence & Matlab.
- RF Transceiver Design, modeled on Agilent Advanced Design System (ADS).
- Signal level indicator, Design of Digital Systems, modified, analyzed and generated a sound signal by converting into digital form on the FPGA board. VHDL and FPGA Board.
- Soft Radio Receiver using DSP, generating And Analyzing AM and FM Signal Using DSP board.
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